1. Field of the Invention
This disclosure relates to a layout for a semiconductor memory device, and more particularly, to a layout for a PMOS-type equalizer and a differential amplifier type data line sense amplifier.
2. Description of the Related Art
FIG. 1 is an internal circuit diagram of a conventional semiconductor memory device (for example, a DRAM).
Referring to FIG. 1, a pair of bit lines BL and BLB are coupled to a pair of local data lines LIO and LIOB through NMOS transistors 101 and 102. Memory cells MC1 and MC2, coupled to word lines WL1 and WL2 and bit lines BL and BLB are arranged in a memory cell array block MCA. The bit lines BL and BLB are coupled to a bit line sense amplifier BLSA which senses and amplifies data of the memory cells MC1 and MC2.
The bit lines BL and BLB are coupled to the local data lines LIO and LIOB through a column selector CS. The column selector CS is coupled to the bit lines BL and BLB and the local data lines LIO and LIOB. The column selector CS includes NMOS transistors 101 and 102 which are gated by a column selection signal CSL. An equalizer EQN for precharging and equalizing the local data lines LIO and LIOB to an internal supply voltage VINT is coupled between the local data lines LIO and LIOB. The equalizer EQN includes equalizing transistors 103, 104 and 105 which are coupled to the local data lines LIO and LIOB and gated by an equalizing signal LIOEQ. The local data lines LIO and LIOB are coupled to a local data sense amplifier LIOSA which senses and amplifies data transferred to the local data lines LIO and LIOB. The local data line sense amplifier LIOSA is illustrated in detail in FIG. 2.
Referring to FIG. 2, the local data line sense amplifier LIOSA includes first and second NMOS transistors 201 and 202 which are gated by the local data lines LIO and LIOB, respectively, a third NMOS transistor 203 which is coupled between the drains of the first and second NMOS transistors 201 and 202 and a ground voltage VSS and which is gated by a sense amplifier enable signal PLSAE, and fourth and fifth NMOS transistors 204 and 205 which are respectively coupled to the drains of the first and second NMOS transistors 201 and 202 and which are gated by the sense amplifier enable signal PLSAE.
The local data line sense amplifier LIOSA transfers data of the local data line LIO to a read global data line RGIO and transfers data of the complementary local data line LIOB to a complementary global data line RGIOB, when the sense amplifier enable signal PLSAE goes “high.”
FIG. 3 illustrates a general layout of a memory cell core area of a DRAM.
Referring to FIG. 3, memory cell array blocks MCA are arranged in the layout. Word line driver blocks SWD are aligned in a direction in which word lines of the memory cell array blocks MCA are arranged, and sense amplifier blocks S/A are aligned in a direction in which bit lines of the memory cell array blocks MCA are arranged.
Each sense amplifier block S/A includes bit line sense amplifiers BLSA. Conjunction blocks CJT are disposed at intersections of the word line driver blocks SWD and the sense amplifier blocks S/A. In each conjunction block CJT, power drivers for driving the bit line sense amplifiers BLSA and ground drivers are alternately arranged.
The equalizer EQN includes NMOS transistors 103, 104 and 105 (see FIG. 1), and the local data line sense amplifier LIOSA includes of NMOS transistors 201, 202, 203, 204 and 205 (see FIG. 2). The reason for implementing the equalizer EQN and the local data sense amplifier LIOSA with NMOS transistors 103, 104, 105, 201, 202, 203, 204 and 205 is so that the equalizer EQN and the local data sense amplifier LIOSA can be disposed in the sense amplifier block S/A in order to reduce the size of the memory cell core area.
If the equalizer EQN for precharging and equalizing the local data lines LIO and LIOB is implemented by NMOS transistors 103, 104 and 105, the local data lines LIO and LIOB can be completely precharged.
FIG. 4 illustrates a simulation result of precharging the local data lines LIO and LIOB using the NMOS type equalizer EQN.
Referring to FIG. 4, in a first precharge period I, when an equalizing signal LIO goes “high,” the NMOS transistors 103, 104 and 105 are turned on, and the local data lines LIO and LIOB become VINT-Vthn when an internal supply voltage VINT falls by an amount corresponding to a threshold voltage Vthn of the NMOS transistors 104 and 105. As the first precharge period I is extended, the local data lines LIO and LIOB are precharged to the internal supply voltage level VINT due to a leakage current component of the NMOS transistors 104 and 105.
In a first sensing period I, memory cell data transferred to the local data lines LIO and LIOB is sensed.
Then, in a second precharge period II, the local data lines LIO and LIOB are precharged to the voltage VINT-Vthn. However, since the voltage of the local data line LIO sensed and amplified in the first sensing period I is similar to the voltage of VINT, the NMOS transistor 104 is not completely turned on. Accordingly, the local data line LIO cannot be precharged to the same voltage VINT-Vthn as that of the complementary local data line LIOB.
This is because the local data lines LIO and LIOB are precharged to the high internal supply voltage VINT by the NMOS transistors 104 and 105 of the equalizer EQN during the first precharge period I when the first sensing period I is started.
In a second sensing period II, the memory cell data transferred to the local data lines LIO and LIOB are sensed. Then, in a third precharge period III, the local data lines LIO and LIOB are precharged to the voltage VINT-Vthn.